View FAN7393AMX12_7927893.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? half-bridge gate drive ic fan7393a ? rev. 1.0.1 july 2012 fan7393a half-bridge gate drive ic features ? floating channel for bootstrap operation to +600v ? typically 2.5a/2.5a sourcing/sinking current driving capability ? extended allowable negative v s swing to -9.8v for signal propagation at v bs =15v ? high-side output in phase of in input signal ? 3.3v and 5v input logic compatible ? matched propagation delay for both channels ? built-in shutdown function ? built-in uvlo functions for both channels ? built-in common-mode dv/dt noise cancelling circuit ? internal 400ns minimum dead time at r dt =0 ? ? programmable turn-on delay control ? (dead-time) applications ? high-speed power mosfet and igbt gate driver ? induction heating ? high-power dc-dc converter ? synchronous step-down converter ? motor drive inverter description the fan7393a is a half-bridge gate-drive ic with shut - down and programmable dead -time control functions that can drive high-speed mosfets and isolated gate bridge transistors (igbts) operating up to +600v. it has a buffered output stage with all nmos transistors designed for high-pulse-current driving capability and minimum cross-conduction. fairchild?s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circum - stances. an advanced level-shift circuit offers high-side gate driver operation up to v s =-9.8v (typical) for v bs =15v. the uvlo circuit prevents malfunction when v dd and v bs are lower than the specified threshold voltage. the high-current and low-output voltage drop feature makes this device suitable for diverse half- and full- bridge inverters; motor drive inverters, switching mode power supplies, induction heating, and high-power dc- dc converter applications. ordering information 14-sop part number package operating temperature packing method fan7393amx 14-soic -40c to +125c ta p e & r e e l
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 2 fan7393a ? half-bridge gate drive ic typical appli cation diagrams figure 1. typical application circuit internal block diagram figure 2. functional block diagram +15v up to 600v pwm shutdown pwm ic control r dt d boot c boot r1 r boot lo com v b v s v dd sd in dt nc 13 nc nc ho v ss nc 12 14 11 10 9 8 2 3 1 4 7 5 6 load r2 fan7393a uvlo driver pulse generator 7 5 13 11 in v dd com v b v s r r s q driver hs(on/off) ls(on/off) dt ho lo noise canceller 6 12 v ss sd 5v 2 1 4 3 pin 8, 9, 10 and 14 are no connection r dtint 250k delay uvlo schmitt trigger input shoot-through prevention dead-time { dtmin=400ns } vss/com level shift 250k
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 3 fan7393a ? half-bridge gate drive ic pin configuration figure 3. pin configurations (top view) pin definitions pin # name description 1 in logic input for high-side and low-side gate driver output, in-phase with ho 2 sd logic input for shutdown 3 v ss logic ground 4 dt dead-time control with external resistor (referenced to v ss ) 5 com ground 6 lo low-side driver return 7 v dd supply voltage 8 nc no connection 9 nc no connection 10 nc no connection 11 v s high-voltage floating supply return 12 ho high-side driver output 13 v b high-side floating supply 14 nc no connection lo nc fan7393a in ho dt nc nc v dd com v b v s v ss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sd nc
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 4 fan7393a ? half-bridge gate drive ic absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera - ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi - tion, extended exposure to stresses above the recommended operating conditions may affe ct device reliability. the absolute maximum ratings are stress ratings only. t a =25c unless otherwise specified. notes: 1. this ic contains a shunt regulator on v bs . this supply pin should not be driven by a low-impedance voltage source greater than v shunt specified in the electrical characteristics section. 2. mounted on 76.2 x 114.3 x 1.6mm pcb (fr-4 glass epoxy material). 3. refer to the following standards: ? jesd51-2: integral circuits thermal test method environmental conditions - natural convection, and ? jesd51-3: low effective thermal conductivity test board for leaded surface mount packages. 4. do not exceed maximum p d under any circumstances. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual dev ice operation. recommended operating conditions are specified to ensure optimal performa nce to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol characteristics min. max. unit v b high-side floating supply voltage -0.3 625.0 v v s high-side floating offset voltage (1) v b -v shunt v b +0.3 v v ho high-side floating output voltage v s -0.3 v b +0.3 v v lo low-side output voltage -0.3 v dd +0.3 v v dd low-side and logic fixed supply voltage -0.3 25.0 v v in logic input voltage (in) -0.3 v dd +0.3 v v sd logic input voltage ( sd ) v ss 5.5 v dt programmable dead-time pin voltage -0.3 v dd +0.3 v v ss logic ground v dd -25 v dd +0.3 v dv s /dt allowable offset voltage slew rate 50 v/ns p d power dissipation (2, 3, 4) 1 w ? ja thermal resistance 110 ? c/w t j junction temperature +150 ? c t stg storage temperature -55 +150 ? c symbol parameter min. max. unit v b high-side floating supply voltage v s +10 v s +20 v v s high-side floating supply offset voltage 6-v dd 600 v v ho high-side output voltage v s v b v v dd low-side and logic fixed supply voltage 10 20 v v lo low-side output voltage com v dd v v in logic input voltage (in) v ss v dd v v sd logic input voltage ( sd ) v ss 5 v dt programmable dead-time pin voltage v ss v dd v v ss logic ground -5 +5 v t a operating ambient temperature -40 +125 ? c
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 5 fan7393a ? half-bridge gate drive ic electrical characteristics v bias (v dd , v bs )=15.0v, v ss =com=0v, dt=v ss , and t a =25c unless otherwise specified. the v in and i in parameters are referenced to v ss /com and are applicable to the respective input leads: in and sd . the v o and i o parameters are referenced to com and are applicab le to the respective output leads: ho and lo. note: 5 these parameters are guaranteed by design. symbol characteristics test condition min. typ. max. unit power supply section i qdd quiescent v dd supply current v in =0v or 5v 600 1000 ? a i qbs quiescent v bs supply current v in =0v or 5v 55 100 ? a i pdd operating v dd supply current f in =20khz, no load 1.0 1.6 ma i pbs operating v bs supply current c l =1nf, f in =20khz, rms 450 800 ? a i sd shutdown mode supply current sd =v ss 650 1000 ? a i lk offset supply leakage current v b =v s =600v 10 ? a bootstrapped supply section v dduv+ v bsuv+ v dd and v bs supply under-voltage ? positive-going threshold voltage v in =0v, v dd =v bs =sweep 7.8 8.8 9.8 v v dduv- v bsuv- v dd and v bs supply under-voltage ? negative-going threshold voltage v in =0v, v dd =v bs =sweep 7.3 8.3 9.3 v v dduvh - v bsuvh v dd and v bs supply under-voltage lockout hysteresis voltage v in =0v, v dd =v bs =sweep 0.5 v shunt regulator section v shunt shunt regulator clamping voltage for v bs v bs =sweep, i shunt =5ma 21 23 25 v input logic section v ih logic ?1? input voltage for ho & logic ?0? for lo 2.5 v v il logic ?0? input voltage for ho & logic ?1? for lo 0.8 v i in+ logic input high bias current v in =5v, sd =0v 20 50 ? a i in- logic input low bias current v in =0v, sd =5v 3 ? a r in logic input pull-down resistance 100 250 k ? v sdclamp shutdown ( sd ) input clamping voltage (5) 5.0 5.5 v sd + shutdown ( sd ) input positive-going threshold 2.5 v sd - shutdown ( sd ) input negative-going threshold 0.8 v r psd shutdown ( sd ) input pull-up resistance 100 250 k ? gate driver output section v oh high-level output voltage (v bias - v o ) no load (i o =0a) 1.5 v v ol low-level output voltage no load (i o =0a) 100 mv i o+ output high, short-circuit pulsed current (5) v ho =0v, v in =5v, ? pw ? 10s 2.0 2.5 a i o- output low, short-circuit pulsed current (5) v ho =15v, v in =0v, ? pw ? 10s 2.0 2.5 a v ss /com v ss -com/com-v ss voltage endurability (5) -5.0 5.0 v v s allowable negative v s pin voltage for in signal propagation to ho -9.8 -7.0 v
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 6 fan7393a ? half-bridge gate drive ic dynamic electrical characteristics v bias (v dd , v bs )=15.0v, v ss =com=0v, c l =1000pf, dt=v ss, and t a =25c, unless ot herwise specified. note: 6 the turn-on propagation delay includes dead time. symbol parameter conditions min. typ. max. unit t on turn-on propagation delay (6) v s =0v, r dt =0 ? 530 730 ns t off turn-off propagation delay v s =0v 130 250 ns t sd shutdown propagation delay 140 210 ns mt on delay matching, ho and lo turn-on 0 90 ns mt off delay matching, ho and lo turn-off 0 40 ns t r turn-on rise time v s =0v 25 50 ns t f turn-off fall time v s =0v 15 35 ns dt dead time: lo turn-o ff to ho turn-on, ho turn-off to lo turn-on r dt =0 ? 300 400 500 ns r dt =200k ? 4 5 6 s mdt dead-time matching=|dt lo-ho - dt ho-lo | r dt =0 ? 0 40 ns r dt =200k ? 0 500 ns
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 7 typical characteristics figure 4. turn-on propagation delay vs. temperature figure 5. turn-off propagation delay vs. temperature figure 6. turn-on rise time vs. temperature figure 7. turn-off fall time vs. temperature figure 8. dead time (r dt =0 ? ) vs. temperature figure 9. dead time matching (r dt =0 ? ) vs. temperature -40 -20 0 20 40 60 80 100 120 350 400 450 500 550 600 650 700 750 high-side low-side t on [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 50 100 150 200 250 high-side low-side t off [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 high-side low-side t r [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 high-side low-side t f [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 300 350 400 450 500 dt1 dt2 dt [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 mdt [ns] temperature [c]
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 8 typical characteristics (continued) figure 10. dead time (r dt =200k ? ) vs. temperature figure 11. dead-time matching (r dt =200k ? ) vs. temperature figure 12. delay matching vs. temperature figure 13. dead time vs. r dt figure 14. shutdown propagation delay vs. temperature figure 15. shutdown mode supply current vs. temperature -40 -20 0 20 40 60 80 100 120 4.0 4.5 5.0 5.5 6.0 r dt =200k ? dt1 dt2 dt [ ? s] temperature [c] -40 -20 0 20 40 60 80 100 120 -500 -250 0 250 500 mdt [ns] temperature [c] r dt =200k ? -40 -20 0 20 40 60 80 100 120 -100 -75 -50 -25 0 25 50 75 100 mton mtoff delay matching [ns] temperature [c] 0 50 100 150 200 0 1 2 3 4 5 6 dt [ ? s] rdt [k ? ] -40 -20 0 20 40 60 80 100 120 100 120 140 160 180 200 high-side low-side t sd [ns] temperature [c] -40-20 0 20406080100120 300 400 500 600 700 800 900 1000 i sd [ ? a] temperature [c]
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 9 typical characteristics (continued) figure 16. quiescent v dd supply current vs. temperature figure 17. quiescent v bs supply current vs. temperature figure 18. operating v dd supply current vs. temperature figure 19. operating v bs supply current vs. temperature figure 20. v dd uvlo+ vs. temperature figure 21. v dd uvlo- vs. temperature -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 i qbs [ ? a] temperature [c] -40 -20 0 20 40 60 80 100 120 300 400 500 600 700 800 900 1000 i qdd [ ? a] temperature [c] -40 -20 0 20 40 60 80 100 120 700 800 900 1000 1100 1200 1300 i pdd [ ? a] temperature [c] -40 -20 0 20 40 60 80 100 120 200 300 400 500 600 700 800 i pbs [v] temperature [c] -40 -20 0 20 40 60 80 100 120 7.5 8.0 8.5 9.0 9.5 10.0 v dduv+ [v] temperature [c] -40 -20 0 20 40 60 80 100 120 7.5 8.0 8.5 9.0 9.5 10.0 v dduv- [v] temperature [c]
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 10 typical characteristics (continued) figure 22. v bs uvlo+ vs. temperature figure 23. v bs uvlo- vs. temperature figure 24. high-level output voltage vs. temperature figure 25. low-level output voltage vs. temperature figure 26. logic high input voltage vs. temperature figure 27. logic low input voltage vs. temperature -40 -20 0 20 40 60 80 100 120 7.5 8.0 8.5 9.0 9.5 10.0 v bsuv+ [v] temperature [c] -40 -20 0 20 40 60 80 100 120 7.5 8.0 8.5 9.0 9.5 10.0 v bsuv- [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0.0 0.5 1.0 1.5 2.0 high-side low-side v oh [v] temperature [c] -40 -20 0 20 40 60 80 100 120 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 high-side low-side v ol [v] temperature [c] -40 -20 0 20 40 60 80 100 120 1.0 1.5 2.0 2.5 3.0 v ih [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0.5 1.0 1.5 2.0 2.5 3.0 v il [v] temperature [c]
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 11 typical characteristics (continued) figure 28. logic input high bias current vs. temperature figure 29. allowable negative v s voltage vs. temperature figure 30. turn-on propagation delay vs. supply voltage figure 31. turn-off propagation delay vs. supply voltage figure 32. turn-on rise time vs. supply voltage figure 33. turn-off fall time vs. supply voltage -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 i in+ [ ? a] temperature [c] -40 -20 0 20 40 60 80 100 120 -13 -12 -11 -10 -9 -8 -7 v s [v] temperature [c] 10 12 14 16 18 20 350 400 450 500 550 600 650 700 750 high-side low-side t on [ns] supply voltage [v] 10 12 14 16 18 20 50 100 150 200 250 high-side low-side supply voltage [v] t off [ns] 10 12 14 16 18 20 0 10 20 30 40 50 high-side low-side t r [ns] supply voltage [v] 10 12 14 16 18 20 0 5 10 15 20 25 30 35 high-side low-side t f [ns] supply voltage [v]
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 12 typical characteristics (continued) figure 34. quiescent v dd supply current vs. supply voltage figure 35. quiescent v bs supply current vs. supply voltage figure 36. high-level output voltage vs. supply voltage figure 37. low-level output voltage vs. supply voltage 10 12 14 16 18 20 0 20 40 60 80 100 i qbs [ ? a] supply voltage [v] 10 12 14 16 18 20 300 400 500 600 700 800 900 1000 i qdd [ ? a] supply voltage [v] 10 12 14 16 18 20 0.0 0.5 1.0 1.5 2.0 high-side low-side v oh [v] supply voltage [v] 10 12 14 16 18 20 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 high-side low-side v ol [v] supply voltage [v]
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 13 fan7393a ? half-bridge gate drive ic switching time definitions figure 38. switching time test circuit figure 39. input / output timing diagram figure 40. switching time waveform definition +15v sd 10 f 100nf 1nf 1nf +15v 100nf lo 10 f lo com v b v s v dd sd in dt nc 13 nc nc ho v ss nc 12 14 11 10 9 2 3 1 4 7 5 6 8 in ho lo sd dt1 dt2 dt1 dt2 dt1 shutdown shutdown dt1 dt2 in ho lo 10% 90% 50% 50% 90% 10% t off 10% 90% t f t r 10% 90% t r t f t off t on t on
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 14 fan7393a ? half-bridge gate drive ic figure 41. shutdown waveform definition figure 42. dead-time waveform definition figure 43. delay matchi ng waveform definition 90% 50% t sd ho or lo sd mdt= dt lo-ho - dt ho-lo ho lo 10% 90% 90% 10% t off dt lo-ho dt ho-lo in 50% 50% t off 50% in(ho) 50% 90% 90% 10% 10% in(lo) mt on mt off ho lo 50% 50%
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 15 fan7393a ? half-bridge gate drive ic package dimensions figure 49. 14-lead, small outline integrated circuit (soi c), non-jedec, .150-inch narrow body, 225sop package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, ? specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . notes: a) this drawing complies with jedec ms-012 except as noted. b) this dimension is outside the jedec ms-012 value. c) all dimensions are in millimeters. d) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. e) landpattern standard: soic127p600x145-14m f) drawing file name and revision : m14crev1 7.62 #1 1.27 1.80 max 1.65 1.45 0.05min 0.10 max c 0.30 0.15 0.51 0.36 pin one indicator 6.00 8.76 8.36 7 8 14 4.15 3.75 1.27 land pattern recommendation (r0.20) detail a see detail a 0.90 0.50 (r0.10) 8?? top view side view end view (0.27) 0.20 cba c b a 0.36 seating plane gage plane 1.70 1.27 5.60 0.65 b b b #1
fan7393a ? half-bridge gate drive ic ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan7393a ? rev. 1.0.1 16

▲Up To Search▲

Price & Availability of FAN7393AMX12

	To Download FAN7393AMX12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .